ASIC IP and Subsystems RTL Design Lead

Minimum qualifications: Bachelor's degree in Computer Science, Electrical Engineering, or equivalent practical experience. 14 years of experience working on multiple SoCs with silicon success. Experience with Verilog or System verilog language. Experience in high-performance design, multi-power domains with clocking. Preferred qualifications: Experience in STA closure, DV test-plan review, and coverage analysis of the sub-system and chip level verification. Knowledge of one or more of the follo…