ASIC Verification EEJ 2026
Summary
Verifies automotive ASICs and SoCs using SystemVerilog/UVM, formal methods, and coverage-driven flows, then hands off designs for tape-out.
Job DescriptionTasks : Verification of SoCs, automotive ASICs, subsystems, IPs.Application of Metric-driven Verification (MDV) and/or Formal Verification methodologiesDeveloping and tracking of Verification plansDevelop verification environments from scratchCreate VIPIntegration of VIP („Verification-IP“)Measure and analyze regression resultsContinuous improvement of verification methods/tools/flows/processes together with EDA partners Requirement:5 to 10 years of Experience in Digital RTL verification using System Verilog and UVM.Sound knowledge of constrained random verification, UVM/OVMSound knowledge in System Verilog.Experience of developing functional coverage code, coverage analysis.Experience of developing verification environments from scratch is desirable.Good hands on experience with cadence/Synopsys/Mentor tools.Exposure to configuration management, bug tracking tool etc.Knowledge of scripting language, Perl TCL etc.Good experience with AMBA protocolsWorking knowledge on ARM processor-based subsystem/SoC verificationFormal verification experience is a desirable but not must.Must have been a part of one or more ASIC/SoC tape outs.Knowledge of VHDL/VERILOG.SPECMAN knowledge is a desirable but not must
BE / B.Tech / ME / M.Tech (Electronics and Communication)
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