Contract Hardware Engineer Mid- 26-18015
Summary
Contract role designing ASIC RTL-to-physical implementations, writing synthesis constraints, and performing static timing analysis for a hardware engineering team.
$65-$70 per hour San Jose, CA Contract Duration: 12 months Details: Need Design Engineer with very strong experience Timing Constraints Writing. (this must reflect in resume) RTL to Physical Design (RTL2PD) stage experience RTL2PD Design Engineer (ASIC) MUST HAVE: RTL Synthesis, Constraint writing, validation, Static timing Analysis What candidate will Be Doing RTL Synthesis, Constraint writing, validation, Static timing Analysis Writing Scripts/Modifying scripts for RTL synthesis, SDC creati…