CPLD/FPGA 韌體工程師(伺服器系統) Staff/Sr. CPLD/FPGA Firmware Engineer

The Staff/Sr. Engineer, CPLD will be based in Taiwan Taipei Wugu Site. The Staff/Sr. Engineer, CPLD performs the responsibility for CPLD programming and validation in Server/Storage Projects request.

What a typical day looks like:
1. Skilled FPGA/CPLD Design Engineer with strong capabilities in Server/Storage system and hardware-level design.
2. Responsible for development and integration of CPLD/FPGA that implement functionality on prototypes: spanning from low-level hardware sequence control, logic control & status for embedded systems, to high-speed links, to high level IP blocks, to custom hardware-accelerated algorithms & filters.
3. Work closely with Hardware, BIOS, BMC and Firmware team for CPLD/FPGA development.
4. Designing validation plan and development spec.
5. Debugging platform and systems issues.

主要工作內容:

• 負責伺服器及儲存系統之 FPGA／CPLD 設計與硬體開發。
• 負責 CPLD／FPGA 功能開發與整合，涵蓋硬體時序控制、邏輯控制、系統狀態管理、高速介面、IP 模組及客製化硬體加速演算法開發。
• 與硬體、BIOS、BMC 及韌體團隊密切合作，共同完成 FPGA／CPLD 開發與系統整合。
• 制定驗證計畫及技術規格文件。
• 執行平台及系統問題分析、除錯與改善。
• 參與產品開發、驗證及量產導入，確保設計符合產品需求與品質要求。

The experience we are looking to add to our team:
1. 3-10 years of working experience in Firmware development.
2. Familiar in Verilog RTL language. Experienced with CPLD/FPGA development on Lattice, Altera and Xilinx devices.
3. Experience with I2C, SPI, LPC, UART, PCIe protocol design
4. Experience with verification methodologies, RTL and gate level simulations and debug.
5.Good problem-solving skills.

我們期待您具備以下條件:
3至10年以上韌體開發相關工作經驗。
熟悉 Verilog RTL 設計語言，具 Lattice、Altera 或 Xilinx 等 FPGA／CPLD 平台開發經驗。
具 I²C、SPI、LPC、UART、PCIe 等通訊協定設計與開發經驗。
熟悉驗證方法學、RTL Simulation、Gate-Level Simulation 及相關除錯技術。
具良好的問題分析與解決能力。