CPU Clock Design Engineer - Jitter, CTS & Low-Power Timing in , us

Qualcomm in Santa Clara, CA is seeking a Physical Design Clock Engineer to collaborate with microarchitecture, RTL, CAD, block and top-level physical design teams to create best-in-class clocking solutions for next CPUs.
The role requires expertise in clock , jitter analysis, and low-skew/low-power design, with responsibilities spanning PLLs, CTS, and clock distribution methodology across CPU designs.

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