<Data Center>BE integrator
Posted Updated
Description
1. Chip integration design
2. Familiar with test mode and DFT/MBIST
3. Familiar with STA and timing signoff
4. System bus and peripheral designs
5. SoC system IO/clock/reset/test mode
Requirements
1. Chip integration design
2. Familiar with test mode and DFT/MBIST
3. Familiar with STA and timing signoff
4. System bus and peripheral designs
5. SoC system IO/clock/reset/test mode
Education: Master's Degree
