<Data Center>DFT Design Engineer

We are looking for a Senior DFT Engineer to define and implement DFT architectures for data center ASIC products. The role involves developing test strategies, integrating DFT features, and improving test coverage for mass production. You will work closely with design teams to ensure robust DFT solutions, yield improvement, and quality.

Key Responsibilities
•_x0001_Develop and optimize test strategies to achieve coverage and manufacturing goals; analyze and improve test coverage.
•_x0001_Integrate DFT features at RTL and gate-level, supporting both top and block-level DFT planning and implementation.
•_x0001_Perform ATPG, fault simulation, and coverage analysis.
•_x0001_Collaborate with BE and PD teams to ensure DFT-friendly timing and support IR convergence in test mode.
•_x0001_Lead silicon bring-up and debug of test features; conduct failure and yield analysis.
•_x0001_Work with product teams to facilitate pattern generation, validation, and DPPM improvement.

Requirements

•_x0001_Experience: 3+ years of hands-on experience in DFT architecture and implementation for SoC/ASIC.
•_x0001_Tools: Practical experience with DFT EDA tools (such as Tessent, TestMAX) including scan insertion, ATPG, MBIST, boundary scan, and coverage debug.
•_x0001_Knowledge: Familiarity with RTL and gate-level integration of DFT features.Working knowledge of test strategies, coverage analysis, and fault simulation.Experience with memory BIST, boundary scan, JTAG/IJTAG, and system test concepts
•_x0001_Education: B.S./M.S. in Electrical Engineering, Computer Engineering, or a related field.
Preferred Qualifications
•_x0001_Experience with advanced technology nodes (< 7nm).
•_x0001_Strong collaboration skills for working with cross-functional and global teams.
•_x0001_Excellent problem-solving skills to analyze CAD/DFT issues and implement solutions.

Location: Hsinchu, Taipei, Singapore.