<Data center>Digital IC Design Engineer_Taipei (SOC BE)

1. Digital IC design BE flow/methodology improvement
2. Digital IC design BE task execution and management
(2.a) Physical aware synthesis, DFT-SCAN, DFT-MBIST insertion
(2.b) STA timing analysis & fixing
(2.c) Netlist level QC. e.g., CLP.
3. Design and clock structure optimization for PPA (Performance, Power, Area). Work closely with FE RTL designers and PD APR teams
4. Job grade will be offered according to the candidate’s experience and expertise

Requirements

1. MS degree of engineering or above
2. Over 2 years of SOC digital design experience, with primary responsibility in one or more of the following BE tasks:
(2.a) Physical aware synthesis (1+ years)
(2.b) STA timing analysis & fixing (1+ years)
(2.c) Pre/Post-netlist QC. e.g., CLP (1+ years)
(2.d) DFT-SCAN, DFT-MBIST insertion and pattern generation (1+ years)
3. Strong communication skill across teams
4. Experience in any of the following is a plus:
(4.a) SOC clock/reset structure and design constraints
(4.b) Lower power design & integration flows
(4.c) APR physical design implementation flows
(4.d) Floor Plan, Package design
Education: Master's Degree