<Data Center>IC Design Verification Engineer

Co-work with algorithm, digital/analog design, firmware, AI tool teams.
0+ ~ 10+ Years Experience in:
Agentic AI Workflow/Tool Evaluation/Deployment
Data Center & High-Speed SerDes Design Verification Plan & Project Execution
Automotive Design Verification Plan & Project Execution
5G/6G Wireless Communication Design Verification Plan & Project Execution
Satellite/NTN Communication Design Verification Plan & Project Execution
Processor Platform/Peripherals Design Verification Plan & Project Execution
Subsystem / System Level Design Verification Plan & Project Execution

Requirements

01._x0001_Must be proficient in at least one of the following programming languages: Verilog / System Verilog / C++ / Python.
02._x0001_Must have continuous improvement / innovation / teamwork mindsets.
03._x0001_Good at debug ability / problem-solving / issue analysis.
[Optional]
01._x0001_Experience with UVM (Universal Verification Methodology).
02._x0001_Experience with assertion and formal verification.
03._x0001_Experience with IC design flow, logic design, and computer architecture.
04._x0001_Experience with platform (e.g., bus, clock, power, reset, dma, etc).
05._x0001_Experience with mixed signal design and verification.
06._x0001_Experience with communication system and signal processing.
07._x0001_Experience with subsystem / chip level verification.
08._x0001_Experience with well-organized and comprehensive verification planning.
09._x0001_Experience with verification methodology.
10._x0001_Experience with technical management, project management, and team/people management.
Education: Master's Degree