<Data center>Senior Low Power Design Methodology Engineer

• Drive and deploy advanced SoC-level power optimization techniques for next-generation data center products; collaborate with RTL, synthesis, and physical design teams to architect and implement low-power features.
• Perform power estimation and analysis across design stages (RTL → gate-level → post-layout) and provide actionable recommendations to reduce power.
• Partner with tier-1 customers to define power specifications and deliver power estimates
• Support silicon power correlation and power-related debug during sample back

Requirements

• Master’s degree with 3+ years of relevant industry experience in Electrical Engineering, Computer Engineering, or a related field.
• Hands-on experience with low-power methodologies for advanced-node (≤7 nm) SoCs, such as multi-power-domain design, DVFS (dynamic voltage and frequency scaling), and AVS (adaptive voltage scaling).
• Experience with power analysis/estimation tools and proficiency in scripting (e.g., Python) to automate data processing and reporting.
• Familiarity with the end-to-end SoC design flow, from architecture and RTL through synthesis, gate-level netlist, and silicon bring-up.
• Knowledge of power delivery networks (PDN), IR drop, and signal integrity is a plus.
• Strong English communication skills are a plus.
Education: Master's Degree