<Data center>Senior Package Integrator

- Coordinate the development of advanced packaging solutions (e.g., CoWoS, 2.5D/3.5D integration, and chiplet-based architectures) by driving cross-functional alignment on technical requirements, interfaces, and deliverables.
- Lead SoC floorplanning to optimize PPA (power, performance, and die area), balancing timing, congestion, power-domain boundaries, and PDN/thermal considerations.
- Partner with the package team to define and refine an optimized ball/bump map that meets SI/PI, current capacity, manufacturability, and reliability requirements.

Requirements

- Master’s degree in Electrical Engineering, Mechanical Engineering, or equivalent practical experience.
- 7+ years of chip design/integration experience.
•_x0001_Including 3+ years of package design and SoC floorplan optimization.
- Strong knowledge and hands-on experience in SoC floorplanning, IO placement, ball/bump planning, and power delivery network (PDN) planning.
- Familiarity with advanced packaging technologies such as CoWoS, 3.5D integration, and chiplet architectures.
- Proven ability on leading teams with schedule planning, issue tracking, and cross-functional coordination.
- Solid understanding of Signal Integrity (SI) and Power Integrity (PI) principles is a plus.
- Familiarity with interposer-based solutions and/or EMIB is a plus.
Education: Master's Degree