<Data center>Senior SerDes Design Verification Engineer

1. SerDes design verification in I/O Chiplet to collaborate with analog/digital/algorithm design teams and system application team from prototype test chip to mass production.
2. Responsible for implementing test script or designing test firmware for SerDes Analog IP quailification and PHY performance validation
3. Responsible for establishing automatic test program and data analysis for SerDes Analog IP and PHY characterization and failure analysis.

1. Master's degree in electrical engineering, communication, or equivalent
2. Knowledgeable about Wireline Communication principle, such as SerDes, Ethernet, PCIe, USB, MIPI, and etc.
3. Experience with test script development or test firmware design
4. Knowledgeable about analog or digital Frontend principle, such as Rx, Tx, PLL, CDR, EQ, and etc is plus
5. Experience with automated test development is a plus
6. Experience with test instruments (PPG, BERT, Scope, etc) operation is a plus
7. Familiar with Python, Visual Studio and MATLAB is a plus.