<Data Center> Sr./ Staff AI Server Platform Architect

About the Role
We are seeking an AI Server Platform Architect to own the compute building block of the rack: xPU (ASIC) platform integration and the server board/compute tray that carries it. You will define board and tray architecture, xPU platform requirements and tray-level power and thermal envelopes, and support chassis integration with the Rack Thermal & Mechanical Architect. You will also lead system bring-up, validation, reliability and safety/EMC compliance for the team, co-own rack bring-up with the Rack System Architect and Technical Project Manager, and work closely with third-party ODM vendors and CSP/OEM and Datacenter customers to drive co-engineering.

Key Responsibilities

• xPU integration: Own platform-level requirements for the xPU (power, thermal, signal integrity, form factor) with the silicon team.
• Compute tray architecture: Define server board and tray architecture (xPU, host CPU, memory, PCIe/NVLink, BMC, on-board power).
• Platform power/thermal: Set tray power and thermal envelopes, power capping and management policy.
• Chassis integration: Support the Rack Thermal & Mechanical Architect on tray envelopes, serviceability, hot-swap and cabling.
• Fabric attach: Support the AI Rack Network Architect on NVLink Fusion and NVLink switch connectivity.
• Bring-up: Lead hands-on system bring-up and debug with firmware, BIOS and BMC teams.
• Validation & reliability: Own the test plan (functional, stress, burn-in, MTBF) and failure analysis.
• Compliance: Drive safety, EMC and regulatory certification (UL/IEC 62368-1, FCC/CE).
• ODM/OEM: Run design reviews and NPI readiness with manufacturing partners.

#LI-JK1

Required Qualifications

• Education: BS/MS in Electrical or Computer Engineering, Computer Science or related field.
• Experience: 8+ years in datacenter server or system platform design.
• Accelerator platforms: GPU/accelerator server design (OAM, HGX, MGX or custom xPU trays).
• Interconnect & memory: PCIe Gen5/6, CXL, DDR/HBM and high-speed signal integrity.
• Management: BMC/OpenBMC, Redfish and firmware enablement.
• Bring-up & debug: Hands-on lab bring-up with scopes, protocol analyzers and power measurement.
• Compliance: Safety, EMC and reliability qualification processes.

Preferred Experience

• Liquid-cooled compute tray design.
• NPI and manufacturing ramp experience with ODMs.
• OCP platform specs (DC-MHS, OAI/OAM).
• Customer-facing platform qualification with CSPs.

Key Interfaces
xPU/silicon team; Rack System, Rack Power, Rack Thermal & Mechanical and AI Rack Network Architects; Rack Management Software Engineers; Technical Project Manager; ODM/OEM partners; compliance labs.