<Data center>TOP Designer & FE Integrator

1. Top design for testing: uArch, design, simulation:
- DFT top, PAD top

2. Top/sensor FE integration and simulation:
- eFUSE
- PVT sensor, aging sensor
- IO integration based on customer requirement

3. Test sequence preparation for Post-Si test and HTOL
4. RFI/RFQ: Sync customer testing structure, IO and sensor requirement

Requirements

1. Familiar with digital IC design, DFT, and STA flow
2. Experienced in SoC architecture, Embedded Processor system architecture design is a plus
3. Experienced in chip integration is a plus
4. Experienced for top design control including power-on-reset sequence, sensor control, top DFT, mix-signal interface design
Education: Master's Degree