Design Engineer ( FV )
Posted Updated 4
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Description
lient Qualcomm
Required Key Words Full Chip FV, RTL - RTL FV, RTL - Netlist FV,
Skills Design Engineer ( FV )
Exp. Level 3.5- Yrs
# of Position 10
Work Location (also mention if we can consider relocation) Bangalore
Max PR for Candidate 12.00 LPA
Interview Mode F2F Interview only
No Telephonic + No Skype
Interview location & Data 5-March -2016 Saturday
Remarks (if any) – deadline to share profiles /walk-in deadline/etc Should have good expertise in Full Chip FV, RTL - RTL FV, RTL - Netlist FV, Conformal ECO, Non-EQ debug