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Design Engineering Intern

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Summary

Design Engineering Intern at SK Hynix Memory Solutions contributing to an ASIC project. Day-to-day work includes coding RTL logic in Verilog/SystemVerilog, running simulations with Synopsys VCS, debugging simulation environments, and managing design databases. 6-month, full-time, 100% onsite internship in San Jose.

About the Company:

At SK Hynix Memory Solution, we're at the forefront of semiconductor innovation, developing advanced memory solutions that power everything from smartphones to data centers. As a global leader in DRAM and NAND flash technologies, we drive the evolution of advancing mobile technology, empowering cloud computing, and pioneering future technologies. Our cutting-edge memory technologies are essential in today's most advanced electronic devices and IT infrastructure, enabling enhanced performance and user experiences across the digital landscape.

We're looking for innovative minds to join our mission of shaping the future of technology. At SK Hynix Memory, you'll be part of a team that's pioneering breakthrough memory solutions while maintaining a strong commitment to sustainability. We're not just adapting to technological change – we're driving it, with significant investments in artificial intelligence, machine learning, and eco-friendly solutions and operational practices. As we continue to expand our market presence and push the boundaries of what's possible in semiconductor technology, we invite you to be part of our journey to creating the next generation of memory solutions that will define the future of computing.

Internship Duration: 6 months

Hours: 40 hours per week

Start Date: Immediately

Team Description:

We are seeking a highly motivated and detail-oriented intern to join our team to contribute to ongoing ASIC project.

Responsibilities:

  • Perform design database management; proper check-in’s of golden files, reverting unused changes, merge different files.
  • Should be able to code RTL logic with Verfilog syntax.
  • Should be able to run simulation using Synopsys VCS.
  • Should be able to debug simulation environment; compilation failure, simulation hang, simulation functional failure, etc.
  • Should be able to communicate with designers, verification engineers, and other team for the correct solution.

Minimum Qualifications:

  • BS/MS degree (completed or in progress) in Electrical Engineering, Electronics, Computer Science, or a related field.
  • Must have proficiency in Verilog, SystemVerilog programming language.
  • Must have good communication within co-working environments.
  • Must have good work ethic, i.e. punctual on deadline, trustworthy commitment on assignment.
  • Must be available to work 40 hours per week, Monday – Friday.
  • 100% onsite commitment for a 6-month duration.

Preferred Qualifications:

  • Have a mindset on problem solving.
  • Understand ASIC/FPGA workflow from concept to real silicon
  • Scripting language skills such as Python, Perl, Tcl, etc.

COMPENSATION: $35/hr - $45/hr

What this application asks

greenhouse

First Name, Last Name, Email, Phone, Resume/CV, Cover Letter

  • Preferred First Name optional
  • LinkedIn Profile optional
  • Website optional
  • When do you graduate? If you have not graduated yet, how do plan to work 40 hours for this internship? written answer
  • This role requires you to work onsite 5 days a week at our San Jose location. Is that a requirement you can meet? choose one
  • Can you complete a 6 month internship starting immediately?
  • What is your current work authorization?
  • Will you now or in the future require sponsorship to work in the U.S.? choose one
  • If you are not located in San Jose, CA are you willing to relocate? choose one

See also