Design Verification Engineer
Summary
Senior engineer verifying semiconductor IPs and SoCs by building verification environments, writing test plans, and catching bugs before tape-out.
Job Title: Design Verification Engineer Location: San Jose, CA Experience: 8 Years Type: Contract Description: This requirement is for a Senior Design Verification (DV) Engineer focused on verifying complex semiconductor IPs and SoCs before silicon fabrication. The client is looking for someone who can independently build verification environments, create test plans, and identify design bugs early in the development cycle. Key Skills Required · 8 years of Design Verification experience in semic…