Design Verification Engineer
Posted Updated 5
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Description
Job Title: Design Verification Engineer
Location: Santa Clara, CA
Duration: 06 months (High Possibility of an extension)
Job Description:
Senior DV engineer responsible for defining and implementing verification methodology and verifying in any of the following key areas of our next generation ASIC:
1. PCIE verification background
2. 400G MAC verification background
All your information will be kept confidential according to EEO guidelines.
