Design Verification Engineer

$70-$85 per hour Santa Clara, CA Contract Duration: 12 Months Top Must Have Skills: Solid minimum 8 years Design Verification Experience Verification Experience with DDR5 Controller /PHY System Verilog /UVM - Language Skills THE ROLE: We are looking for an adaptive, self-motivative Design Verification Engineer to join our growing team. As a key contributor, you will be part of a leading team to drive and improve client's abilities to deliver the highest quality, industry-leading technologie…