DFT Engineer/Design for test
Summary
Designs and implements test solutions for SoC/ASIC chips, focusing on DFT (Design for Test) and ATPG (Automatic Test Pattern Generation) to ensure chip reliability and debug issues.
Role: DFT Engineer/Design for test Office Location: Santa Clara, California Exp: 7yrs No Of position:- 7 Job Description & Skill Requirement: Required Skills & Qualifications • 5 years of hands-on experience in DFT and ATPG for SoC or ASIC designs • Strong understanding of DFT fundamentals including controllability, observability, and scan-based testing • Proven expertise in ATPG pattern generation, analysis, and debug • Experience with MBIST, including memory test architectures and diagnostics…
