DFT Engineer

You will join the Silicon team and work on next-generation AI designs built for data center applications. You'll keep up with the latest DFT industry trends and help bring new techniques and methodologies into the team's practice. You'll collaborate closely with design, verification, physical design and product engineering teams to weave DFT requirements into the overall design process. You'll define and implement DFT architecture and features, support their verification, and build efficient DFT flows that fit smoothly into the silicon design process. You'll integrate third-party IP into the DFT infrastructure, generate structural test vectors, and analyze and improve test coverage. Finally, you'll partner with product and test engineering teams to ensure successful silicon bring-up, helping identify silicon failures and drive yield learning and improvement.

Responsibilities

• Keep up with the latest industry trends in the DFT domain and help adopt new DFT techniques and methodologies
• Work closely with design, verification, physical design and product engineering teams to integrate DFT requirements into the overall design process
• Define and implement DFT architecture and features for next-generation AI designs and support their verification effort
• Develop efficient DFT flows and methodology compatible with silicon design flows
• Work with 3rd party IPs to integrate the provided design into the DFT infrastructure
• Generate structural test vectors, analyze and improve test coverage
• Work with the product and test engineering teams to ensure successful silicon bring-up and help identify silicon failures to enhance yield learning and improvement

Requirements

• Very good understanding of DFT components like JTAG (IEEE 1149.x), IJTAG (IEEE P1687), Core Test (IEEE P1500), SSN (Streaming Scan Network), Test Compression, OCC etc.
• Experience developing DFT specifications and driving the implementation of DFT features
• Experience in MBIST and BISR implementation and verification is desired
• Solid understanding of design verification methodologies for validating DFT features using simulation in pre-silicon designs
• Exposure to STA constraints development and analysis for DFT modes and SDF simulations would be a plus
• Experience in scan based testing and industry standard ATPG tools
• Knowledge of ATPG pattern verification and gate-level simulation flows using Synopsys VCS and Verdi or other EDA tools
• Very good knowledge of digital integrated circuits and systems
• Hands-on experience with Verilog RTL coding and familiarity with System Verilog
• Strong scripting and debugging skills using programming languages like Python, TCL, Perl, Shell etc.
• Exposure to silicon bring-up, post-silicon testing and tester pattern debugging
• Strong problem-solving skills across various levels of design hierarchies
• Great team working and communication skills
• Bachelors or Masters or PhD in Computer Engineering/Electrical Engineering/Electronics Engineering

Benefits

• Flexible working
• Generous annual leave policy
• Private medical insurance
• Health cash plan
• Dental plan
• Pension (matched up to 5%)
• Life assurance
• Income protection
• Generous parental leave policy
• Employee assistance programme
• Healthy food and snacks
• Barista bar