DFT Engineering Leader
You will lead DFT engineering efforts, working on advanced test and design-for-test methodologies for cutting-edge chip designs. You will implement and optimize boundary scan, MBIST, test logic insertion, and JTAG solutions, and develop and validate scan ATPG and compression methodologies. You will conduct DFT and post-gate simulation processes to ensure design robustness, generate and apply DFT constraints for efficient testing, and deliver effective test patterns while collaborating with the test team on ATE debugging. You will use EDA tools like Tessent to enhance test processes and efficiency, and provide technical mentorship and guidance to junior engineers.
Responsibilities
- Implement and optimize boundary scan, MBIST, test logic insertion, and JTAG solutions
- Develop and validate scan ATPG and compression methodologies
- Conduct DFT and post-gate simulation processes to ensure design robustness
- Generate and apply DFT constraints for efficient testing
- Deliver effective test patterns and collaborate with the test team for ATE debugging
- Utilize EDA tools like Tessent to enhance test processes and efficiency
- Provide technical mentorship and guidance to junior engineers
Requirements
- Bachelor/Master/PhD degree in Electrical Engineering or Computer Engineering
- At least 8 years of relevant experience
- Proficiency in synthesis tools such as Genus or Design Compiler
- Experience working closely with designers to create test plans and strategies
- Proven ability to collaborate with implementation teams for DFT insertion and resolve DFT-related timing or congestion challenges
- Highly driven and detail-oriented
Benefits
- Attractive welfare benefits and developmental opportunities such as training and mentoring