Director, Embedded Memory

- Build and maintain memory IP benchmarks - Conduct PPA analysis performance power area yield - Define bitcell selection and peripheral architecture - Drive circuit design and physical implementation - Establish design verification and signoff methodology - Lead integration debug and silicon correlation - Lead memory compiler architecture - Lead presales customer engagements and technical proposals - Lead statistical and Monte Carlo analysis - Manage DFT scan and BIST repair strategy - Manage roadmap schedules dependencies and risks - Mentor and grow memory design engineering team - Optimize Vmin leakage performance area yield - Perform customer issue root cause analysis - Perform silicon validation and test chip development - Represent company in foundry partner meetings and industry conferences - Run what if and sensitivity analysis for architecture tradeoffs - Support customer integration through tapeout and validation - Translate SoC requirements into compiler specifications Perks/Benefits: - Financial benefits - Hybrid office location - Industry conference visibility - Medical benefits - Team leadership development