Distinguished Member of Technical Staff (DMTS) – Process Development, Photolithography, NAND
Summary
Leads long-term photolithography strategy for NAND memory, setting enterprise-wide roadmaps, mentoring engineers, and driving innovation in semiconductor process development.
Job / Role Summary
The DMTS provides enterprise‑level technical leadership, defining photolithography strategy and shaping industry‑relevant technology directions. This role leads & influences development & integration strategy, mentors senior engineers, and drives innovation across development teams.
Main Responsibilities
Sponsor long-range pathfinding initiatives for future nodes and architectures
Establish and steward enterprise‑wide, long‑term photolithography technology vision and strategic roadmaps.
De‑risk novel lithography concepts and platforms.
Serve as a technical authority across R&D and manufacturing.
Influence strategy at executive and industry levels.
Other Responsibilities
Mentor next-generation technical leaders
Steward intellectual property and standards
Set internal technical standards
Integrates AI assisted tools and insights into daily work to improve efficiency, quality, or effectiveness, exercising sound judgment and complying with organizational standards and legal requirements.
Contributes to a culture of continuous improvement by identifying, testing, and sharing AI enabled enhancements within one’s scope of work.
Candidate Profile
Minimum Qualifications / Experience
PhD ≥15 yrs, or Master’s ≥17 yrs, of relevant experience in
Electrical Engineering, Materials Science, Chemical Engineering, Physics, or related field, with demonstrated experience in semiconductor photolithography process development.
Industry recognized innovation leader
Must‑Have Technical Skills
Advanced proficiency in photolithography process & equipment roadmaps; cutting edge photolithography equipment & metrology tools experience
Advanced knowledge in optics, immersion lithography, polarized illumination, and low k1 imaging
Advanced understanding of semiconductor process flows and memory architecture
Multi-node, Multi-site program leadership