DV/ 數位ic 設計工程師 | FC02014140

RTL、Verilog、EDA
Verification of digital design ,most on serdes phy ip using UVM , including
.standard spec study/design feature study
.simple vip creation or third parity vip survey
.vplan define
.building sb/assertion check ,stimulus by constraint random
.create covergroup /assertion cover for  functional coverage
.code coverage
.co –simulation with analog phy