EICDV5235 Design Verification Engineer Onsite

Job Title: Design Verification Engineer EICDV5235

Location: San Jose ,CA , Onsite

Duration: Full Time

12+ years of experience in SOC/IP/block level functional verification using System Verilog/UVM.

• Must have executed at-least 1 to 2 SoC/IP Verification projects on C++ based verification environment

• Knowledge of Ethernet PCS layer, and or OTN G709 is required.

• Strong knowledge of C++ • UVM and System Verilog added advantage.

• Must have worked on development of test plan, testbench components, verification environment, interface agents, Scoreboards.

• Understanding of complete functional verification cycle will be added advantage

• Skills to debug RTL & testbench issues, test failures. • Experience on verification closure by closing Coverage and bug reports

• Understanding of customer dynamic environment change and adopt run time changes in schedule, design etc.

Qualifications:

• B.E., B.TECH, M.E. M. TECH