FPGA ENGINEER (AI ACCELERATOR / VERSAL AI ENGINE)

About the Role:

• FPT Telecom is building the next generation of Edge AI computing solutions. We are looking for a highly skilled FPGA Engineer with specialized experience in AI Acceleration using AMD/Xilinx Versal ACAP architectures. In this role, you will bridge the gap between AI algorithms and hardware execution, developing high-performance, low-latency, and power-efficient AI accelerators for AI Server.

Key Responsibilities:

• AI Hardware Deployment: Compile and deploy AI models (CNNs, Transformers) from frameworks (PyTorch/TensorFlow) to FPGA/SoC hardware using Vitis AI.
• AI Engine (AIE) Programming: Design, implement (in C/C++), and optimize parallel computing algorithms onto the AI Engine array of Xilinx Versal devices.
• Dataflow Optimization: Architect high-throughput data movement between Programmable Logic (PL), Processing System (PS), and AIE using AXI-Stream, DMA, and Network-on-Chip (NoC).
• System Integration: Collaborate with AI Engineers for model quantization (INT8/FP16) and HW Engineers to integrate custom pre/post-processing blocks (Verilog/HLS) into the system.
• Verification & Profiling: Perform hardware-in-the-loop testing, bottleneck analysis, and profiling using Vitis Analyzer on actual evaluation boards.

Requirements

About the Role:

• FPT Telecom is building the next generation of Edge AI computing solutions. We are looking for a highly skilled FPGA Engineer with specialized experience in AI Acceleration using AMD/Xilinx Versal ACAP architectures. In this role, you will bridge the gap between AI algorithms and hardware execution, developing high-performance, low-latency, and power-efficient AI accelerators for AI Server.

Key Responsibilities:

• AI Hardware Deployment: Compile and deploy AI models (CNNs, Transformers) from frameworks (PyTorch/TensorFlow) to FPGA/SoC hardware using Vitis AI.
• AI Engine (AIE) Programming: Design, implement (in C/C++), and optimize parallel computing algorithms onto the AI Engine array of Xilinx Versal devices.
• Dataflow Optimization: Architect high-throughput data movement between Programmable Logic (PL), Processing System (PS), and AIE using AXI-Stream, DMA, and Network-on-Chip (NoC).
• System Integration: Collaborate with AI Engineers for model quantization (INT8/FP16) and HW Engineers to integrate custom pre/post-processing blocks (Verilog/HLS) into the system.
• Verification & Profiling: Perform hardware-in-the-loop testing, bottleneck analysis, and profiling using Vitis Analyzer on actual evaluation boards.