FPGA Timing Specialist

We are looking for a Principal FPGA Timing Specialist to analyse and optimise existing FPGA designs, resolve complex timing failures, and improve the overall compilation workflow.

The role requires approximately 5–6 hours of daily overlap with the Hong Kong engineering team (start of the workday at 8:00–9:00 a.m. Kyiv time)

About Digis
Digis is a global software development company with 200+ specialists delivering custom software development and staff augmentation services to clients in the US, UK, and EU.
We build long-term partnerships and focus on transparency, trust, and measurable business results.

About the project
Company develops FPGA-based hardware that recreates classic video-game systems at the hardware level. The project involves a mature FPGA codebase built on Intel/Altera technology. The main goal is to eliminate timing failures, reduce the number of compilation seeds required for successful builds, and shorten prolonged FPGA build times.

Key responsibilities
Analyse failed timing paths, path delays, clock skew, and routing congestion in Quartus
Review and optimise SDC constraints and static timing analysis results
Refactor Verilog modules and restructure pipelines or FPGA architectures
Resolve complex timing-closure and CDC issues
Optimise high-speed digital interfaces
Reduce compilation iterations and overall FPGA build time
Document identified issues, implemented solutions, and recommended practices

Requirements
3+ years of hands-on Verilog FPGA design experience
Deep practical experience with Intel/Altera FPGA architecture
Upper-Intermediate+ English level

We Offer
20 paid vacation days per year
5 paid sick leaves per year (no medical documents required)
Personalized development plan with training compensation
English courses compensation
Work equipment if needed (PC / laptop / monitor)
Flat and transparent internal communication
Opportunity to switch between projects and technologies within Digis