G260020-Chip Application Front-End Engineer / Manager

Chip Application Front-End Engineer
※ Job Contents:
1. Took responsibility of creating SDC for the complex SoC.
2. Took responsibility of timing analysis with customer.
3. Took responsibility of planning low-power structure and review flow (CPF/UPF).
4. Supported back-end team in post-layout timing closures
5. Supported project team in central tech-library management
6. Run EDA-Tool and GUC in-house design kit.
※ Requirements:
1. Familiar with ASIC Flow.
2. Understood SoC IO structure and experienced of integrating 3rd party IP.
3. Understood physical synthesis flow.
4. 3 years+ exp, have experiences in 16/7/5nm IC design experiences will be plus

Chip Application Front-End Manager/Technical Manager
※ Job Contents:
1. Perform physical synthesis from RTL or gate-to-gate optimization
2. Take responsibility for netlist, SDC and design quality check with customer
3. Chip I/O arrangement and verification with in-house tool
4. Perform low power structure verification (UPF/CPF)
5. Perform power replay and power analysis
6. Review/check implementation quality in each design stage
7. Cooperate with P&R in timing analysis
8. Planning chip level STA (e.g. flatten, HyperScale) strategy and machine arrangement for big design
9. Perform MMMC timing closure and signoff check
10. Schedule and team resource management
※ Requirements:
1. 7 years+ exp, including at least 2 years in a supervisory or management role.
2. Have experiences in 16/7/5nm IC design experiences will be plus