Hardware Design Engineer
Description
You will own board designs end to end — architecture, schematic capture, component selection, layout direction and the design reviews that get them built. This is a hands-on ownership role: the boards you design are the ones the team brings up, debugs and ships.
What you will work on:
Schematic design and ownership of boards for an AI accelerator platform
Component selection and sourcing trade-offs, from silicon to passives
Layout direction and constraint definition, working alongside PCB designers
Design reviews, DFx and the path from prototype through to production
Respins and ECOs driven by test, bring-up and field feedback
Responsibilities:
Schematic capture & ownership: Own the full schematic for assigned boards — architecture, block partitioning, interface definition, power tree and sequencing. Maintain the design through revisions, ECOs and respins.
Component selection: Select and specify components against electrical, thermal, cost, lifecycle and supply constraints. Own the BOM, including second sourcing and obsolescence risk.
Layout direction: Define stackup, placement intent, routing constraints and keep-outs. Review layout against SI, PI, power and thermal requirements, and drive the iterations to closure.
Design verification: Run circuit-level simulation where it matters, build and check timing and interface budgets, and perform worst-case analysis on critical nets and rails.
Cross-functional & lifecycle: Work with SI/PI, power, thermal, mechanical and firmware teams to fold their requirements into the design. Drive formal design reviews, hand the board off cleanly to the bring-up team with the documentation they need, and take it through NPI with manufacturing partners.
Requirements:
5+ years designing complex digital boards — server, datacentre, networking, or comparable high-speed systems
Proven ownership of schematic capture on multi-layer boards carrying high-speed interfaces, from concept to production
Strong grasp of digital and mixed-signal design: power trees, sequencing, clocking, reset, level shifting, interface standards
Comfortable with an EDA suite — Cadence Allegro/OrCAD, Altium, Mentor Xpedition or equivalent
Able to define layout constraints and review layout critically, not just hand it off
Experience carrying a design through multiple revisions and ECOs on the back of test and field feedback
Nice to Have:
Boards carrying PCIe Gen5/Gen6, DDR5/LPDDR, or high-speed SerDes interfaces
High-current power delivery design and PDN-aware layout work
NPI experience with CM or ODM partners, including DFM, DFT and yield feedback
Familiarity with OCP rack-scale platforms and their board form factors
Python scripting for BOM handling, netlist checks and design automation
Why Semidynamics?
Work for one of Europe’s most promising deep-tech semiconductor scale-ups.
Accelerated development path.
4 days per week in the Barcelona office (city center), 1 day WFH.
1 week of work from everywhere in the world.
Competitive package.
A collaborative, technical, and growth-oriented environment that values direct ownership and clear thinking.