Integration Engineer, Packaging Partners

PH-007 | Founding Technical Staff | Boston, MA | Onsite | $120K – $170K base + equity

About Prahelika

Prahelika is building the domestic integration layer: 3D systems in which III-V semiconductors, state-of-the-art silicon, and novel interposers are stacked into one device, each doing what it does best. We co-design the signal path, the power tier, the thermal path, and the manufacturing process, so dies from any foundry become a system that silicon alone cannot deliver. Our first 3D systems serve defense radar and low-Earth-orbit satellite communications; the same platform extends to power electronics, data-center compute, and photonics. Backed by top-tier investors and built by engineers who demonstrated every tier of the stack as measured hardware before the company existed, Prahelika owns the layer between the transistor and the machine. Ultimate electronics through integration.

The role

Whoever owns a design here sees it through fabrication, packaging, measurement, shipping, and the next revision. Our 3D systems are built from dies made at multiple foundries and assembled with partners who run bonding, interposer, and redistribution processes on our behalf until our own line is up. Someone has to hold every one of those handoffs: the design rules, the incoming inspection, the process traveler, the yield data, and the phone call when a lot comes back wrong.

You will be that person. As our first integration engineer, you own the interface between our design team and every foundry, OSAT, and packaging partner we use, from design-rule alignment and tape-out packaging through assembly, inspection, and failure analysis. What you learn about each partner's process becomes the design kit's manufacturing rules.

Required qualifications

• B.S. or M.S. in Electrical, Mechanical, or Materials Engineering with 4+ years in semiconductor packaging, assembly, or foundry interface roles on products that shipped. Equivalent practical experience may substitute for the degree requirement.

• Working knowledge of advanced packaging processes and platforms: die attach, thermocompression or hybrid bonding, flip-chip, redistribution layers, microvias, and wafer thinning; experience handling FCBGA, wMCM, and InFO-class technologies and what each does to yield.

• Experience owning the relationship with an OSAT, foundry, or packaging vendor: design-rule negotiation, tape-out submissions, lot tracking, domestic and global vendor supply-chain tracking, and corrective action.

• Hands-on experience in at least two of the following:

  • Failure analysis and yield learning: cross-section, X-ray, acoustic microscopy, and root-cause on assembly defects.

  • Design-for-manufacturing review of layouts against packaging design rules, and feeding changes back to designers.

  • Multi-material or heterogeneous assembly: compound semiconductor, silicon, and non-organic substrates in one package.

  • Process documentation and traveler, incoming inspection, and quality systems (or the willingness to build them from scratch).

• This role involves work that may be subject to U.S. export-control laws. Prahelika assesses access requirements for the specific work and, where needed, evaluates available government authorization options before granting access to controlled technology. Program assignments are subject to applicable legal requirements.

Preferred qualifications

• Time on a fab or assembly floor, not just at the vendor interface.

• Experience transferring a process from a partner into an in-house line.

• Exposure to advanced technology nodes such as CoWoS, EMIB/EMIB-T, CoPoS, and similar.

Responsibilities

• Own every handoff between our design team and our foundry, OSAT, and packaging partners: design rules, tape-out packages, lot tracking, inspection, and corrective action.

• Translate each partner's process capability into manufacturing rules the design team follows, and push back on the design when it asks for what the process cannot do.

• Run failure analysis and yield learning on returned lots, with the thermal and reliability engineers, and close the loop into the next revision.

• Build the process documentation, travelers, and quality practices that will move with us into our own integration facility.

• Be the person the vendor calls first, and the person our engineers trust to know what actually happened to the lot.

How we work

• Engineers here work across the stack. Siloed circuit, device, and package engineers do not thrive at Prahelika; you will be expected to understand the neighboring disciplines well enough to argue with them.

• AI is a cornerstone of how we engineer. You will build your own workflows with tools such as Claude, ChatGPT, or Codex, compatible with Prahelika's AI ecosystem, with physically grounded checks on what they produce.

• No one is asked to cut a corner they would be ashamed to defend. If a deadline can only be met by skipping a reliability test, the deadline moves, and the engineer who refuses to sign off on something unsound is protected, not punished.

• Credit and authorship follow contribution, not seniority. If your name belongs on the work, it is there.

• Excellence of mind and body is a working condition, not a reward for finishing. Tired decisions end up in hardware; we expect you to sleep, train, and step away, and we do not mistake hours logged for work delivered.

Compensation and benefits

• $120K – $170K base salary plus founding-team equity. Final compensation depends on experience and skills.

• Full medical, dental, and vision coverage with HSA; 401(k) with 4% company match; daily meals.

How to apply

Apply using the form for this role. If available, please include a brief description of one project that best represents your work on this kind of problem; we read that more closely than a cover letter.

Prahelika is an equal opportunity employer. We hire on demonstrated ability, without regard to any protected characteristic.