Инженер-схемотехник / разработчик VHDL (Lattice)
Summary
NetUP (Moscow, remote-friendly) is hiring a circuit-design engineer / VHDL developer to work with Lattice FPGAs. The role focuses on hardware description and FPGA development, with a gross salary of 150,000–250,000 RUB.
Зарплата: 150000–250000 RUR (до вычета налогов)