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愛普科技股份有限公司

Layout-IC佈局工程師

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Description

1. Support the layout project
i. ESD/Latch up
ii. Power block,Band gap/VDC/charge pump
iii. sub-block integration
iv. DRC & LVS verification
2. The following skills would be a strong plus
i. Memory periphery and IO layout
ii. Full chip integration
iii. Skill and pcell experience

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