Memory Controller Digital Engineer

1. Memory system architecture design and RTL implementation on SOC
2. DRAM controller IP development, include high-speed digital PHY, high-efficiency scheduler, low power management unit, and design for test.
3. DRAM controller IP integration (Front-end RTL and design constraint integration, digital IC design flow QC, static timing analysis, project integration task coordination)

#LI-LL1

1. Good knowledge in digital design skill (design for low power, high-speed design, low cost, cross-clock domain design, physical aware design, design for testing)
2. Good knowledge in SOC Digital design integration flow (clock SDC, STA, design QC)
3. Familiarity with the architecture/micro-arch plan and cross-tem coumincation skill with collaboration team
4. Strong problem solving, root causing and debugging skills
5. Good written and oral communication skills
6. Experience with External Memory Interface design is a plus
7. Experience with low power design and power optimization techniques is a plus
8. Experience with high-speed clock design is a plus
9. Familiar with script writing in Python/Perl for data gathering and analysis is a plus