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Cerebras Systems, Inc.

Open 28d

Network Systems Architect

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Summary

Define multi-generation network architecture for Cerebras' AI accelerator systems: set scale-up network roadmaps, derive fabric requirements from AI/HPC workloads, and drive topology, protocol, and switch-ASIC decisions from modeling and simulation through implementation and qualification. Stack spans Ethernet, RDMA/RoCE, InfiniBand, PCIe/CXL, and NCCL/MPI.

You will define multi-generation network architecture and roadmaps. You will derive fabric requirements from workloads, define topology and protocols, evaluate standards-based and custom technologies, use models and prototypes to test designs, and lead specifications and design reviews through implementation and qualification.

Responsibilities

  • Set the architecture and roadmap for scale-up networks and their interfaces
  • Derive bandwidth, latency, ordering, availability, and serviceability requirements from workload and communication choices
  • Define fabric topology, protocols, switch behavior, routing, buffering, flow control, reliability, and fault containment
  • Decide between standards-based technology and custom network designs
  • Use performance models, traffic simulation, prototypes, and lab data to test architecture choices
  • Write architecture and interface specifications
  • Lead design reviews and drive decisions through implementation, bring-up, and qualification

Requirements

  • 12 or more years of relevant industry experience
  • Principal-level technical ownership of a networking, switching, accelerator, or HPC system
  • Expertise in low-latency or proprietary interconnects, fabric protocols, or switch architecture
  • Knowledge of switch pipelines, buffering, routing, flow or congestion control, and reliability
  • Experience deriving network requirements from incomplete workload and system information
  • Knowledge of Ethernet, IP, RDMA, BGP, and EVPN
  • Experience with implementation, modeling, silicon, lab, bring-up, or debugging work
  • Technical decision-making and stakeholder influence
  • Knowledge of accelerator interconnects, switch ASICs, NICs, DPUs, transport offload, collective acceleration, coherent memory, or custom fabrics
  • Knowledge of NCCL, RCCL, MPI, SHMEM, RoCE, InfiniBand, PCIe, or CXL
  • Workload-driven modeling, traffic simulation, emulation, and silicon correlation
  • Knowledge of SerDes, packaging, retimers, cabling, optics, and reach constraints

Skills

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