Onsite_Hardware Design and Failure Analysis Engineer_ San Jose, CA
Posted Updated
Description
Title: Hardware Design and Failure Analysis Engineer
Location: San Jose, CA (Onsite)
Work Arrangement: Onsite
Employment Type: Contract
Duration: 6 Months
Primary Skills: High-Speed System Architecture & Debugging, Power & Signal Integrity (PI/SI) Analysis
Education & Experience: B.S. or M.S. in Electrical Engineering, Computer Engineering, Materials Science, or related field with 10+ years of progressive experience in hardware engineering, board design, or system-level failure analysis.
High-Speed Hardware Expertise: Well versed in modern system architectures (PCIe Gen4/5/6, DDR4/5, HBM, 56G/112G/224G SerDes, optical transceivers).
Power & Signal Integrity: Proven ability to debug complex power distribution network issues/multi-phase VRM transient droop, PMBus/SVID telemetry, switching noise) and high-speed signal integrity anomalies.
Supplier Engagement: Hands-on experience directing external silicon suppliers and analytical Laboratories through component-level physical FA.
Communication: Strong executive presence with proven capability to articulate complex technical findings to cross-functional leaders and enterprise customers.
Preferred Qualifications
Experience leading hardware quality or reliability taskforces for hyperscale cloud service providers (e.g., Microsoft, Meta, Google, AWS).
Knowledge of advanced packaging technologies (chiplets, 2.5D/3D ICs, CoWoS) and silicon failure mechanisms.
Proficiency in writing custom Python or C automation tools to recreate corner-case/intermittent hardware race conditions.
Work Authorization
Applicants must be legally authorized to work in the United States.
Equal Employment Opportunity
Themesoft Inc is an Equal Employment Opportunity employer. We consider qualified applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, age, disability, veteran status, or any other status protected by applicable federal, state, or local law.
Location: San Jose, CA (Onsite)
Work Arrangement: Onsite
Employment Type: Contract
Duration: 6 Months
Primary Skills: High-Speed System Architecture & Debugging, Power & Signal Integrity (PI/SI) Analysis
Education & Experience: B.S. or M.S. in Electrical Engineering, Computer Engineering, Materials Science, or related field with 10+ years of progressive experience in hardware engineering, board design, or system-level failure analysis.
High-Speed Hardware Expertise: Well versed in modern system architectures (PCIe Gen4/5/6, DDR4/5, HBM, 56G/112G/224G SerDes, optical transceivers).
Power & Signal Integrity: Proven ability to debug complex power distribution network issues/multi-phase VRM transient droop, PMBus/SVID telemetry, switching noise) and high-speed signal integrity anomalies.
Supplier Engagement: Hands-on experience directing external silicon suppliers and analytical Laboratories through component-level physical FA.
Communication: Strong executive presence with proven capability to articulate complex technical findings to cross-functional leaders and enterprise customers.
Preferred Qualifications
Experience leading hardware quality or reliability taskforces for hyperscale cloud service providers (e.g., Microsoft, Meta, Google, AWS).
Knowledge of advanced packaging technologies (chiplets, 2.5D/3D ICs, CoWoS) and silicon failure mechanisms.
Proficiency in writing custom Python or C automation tools to recreate corner-case/intermittent hardware race conditions.
Work Authorization
Applicants must be legally authorized to work in the United States.
Equal Employment Opportunity
Themesoft Inc is an Equal Employment Opportunity employer. We consider qualified applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, age, disability, veteran status, or any other status protected by applicable federal, state, or local law.
