Optical Networking Architect / High-Speed Interconnect Chip Technology Lead

Position Title

Optical Networking Architect / High-Speed Interconnect Chip Technology Lead

Role Overview

Own the end-to-end technology leadership of data-center optical interconnect — optical modules, ODSP, and high-speed electrical chips — spanning product definition, system architecture design, algorithm development, opto-electronic co-design, and volume-production delivery. The role requires deep expertise across optical systems, high-speed mixed-signal chips, and algorithms, plus proven ability to lead cross-regional, cross-team joint development.

Key Responsibilities

1. Technology & Product Definition: Drive research and product definition of optical-electronic hybrid solutions, own the technology roadmap.

2. System Architecture & Link Design: Lead link-system modeling, link budget analysis and simulation of Serdes; own ADC/DAC/PLL specification decomposition and mixed-signal architecture design.

3. Chip & Module Delivery: Own requirement analysis, spec definition, design review, application-level testing, and production ramp of 800G/1.6T Driver/TIA and DSP electrical chips; be accountable for delivery quality and schedule.

4. Standards & Ecosystem: Represent the company in standards bodies; contribute technical proposals from requirements, application, and link-design perspectives.

5. Team & Technical Management: Build and lead cross-regional opto-electronic co-design teams; direct technology selection, risk identification/mitigation, and critical-problem resolution.

Qualifications

Must-Have

• Master's degree or above in Communications, Electronic Engineering, Signal Processing, Information Engineering, or relevant subjects, with 10 years of working experience.

• Working experience in optical communications or high-speed interconnect R&D is highly preferred;

• Deep expertise in coherent and IMDD optical systems, ODSP algorithms, and high-speed Serdes architecture;

• Familiar with module form factors from 100G to 1.6T and full productization flows; has led high-speed chips from definition through volume production;

• Proficient in MATLAB/VPI/Python/C system modeling and verification, with FPGA/ASIC algorithm implementation experience (Verilog/HLS);

• End-to-end project leadership from system requirements, spec decomposition, co-design to verification and delivery.

Nice-to-Have

• Standards proposal experience and familiarity with optical physical-layer standards;

• Patents or recognized industry awards;

• Hands-on experience with LPO / optical-electronic hybrid / coherent DSP programs;

• Cross-ecosystem collaboration experience with module vendors, cloud providers, or chip companies.

What We Offer

• Autonomy over core technical directions and exposure to frontier industry topics;

• Competitive compensation and incentives;

• Cross-regional R&D resources and a complete volume-production verification platform.