Package Layout Engineer
Summary
Design advanced multi-die AI accelerator packages, defining substrate stackups, routing high-density channels, and co-engineering with silicon and PCB teams to deliver tapeout-ready layouts.
About the role
Own the physical layout of the advanced packages our AI accelerator silicon ships in. You'll take multi-die 2.5D and 3D packages from bump map through tapeout release — defining substrate and interposer stackups, planning bump and ball maps against the die floorplan, routing high-density escape and HBM-class channels, and building the power delivery that feeds hundreds of amps into the accelerator. You'll sit between the die and the board, co-designing with physical design on one side and PCB layout on the other, and you'll own the design release our substrate suppliers and OSATs build from. When the package is the thing standing between silicon and a working system, this is the role that closes it.
What will you do
- Own package substrate and interposer layout end to end; stackup definition, bump and ball map planning, RDL and escape routing, and design release to substrate suppliers and OSATs
- Own die-to-package-to-board co-design, partnering with physical design on bump placement and floorplan and with PCB layout on the package-board interface
- Close package DRC/LVS and netlist verification against OSAT and substrate vendor design rules, and drive rule negotiation where the design requires it
- Use and develop AI assisted tool flows to accelerate package layout, routing, and signoff timelines
What we're looking for
- Exceptional abilities in advanced package physical layout: multi-die substrate and interposer routing, high-density escape, power and ground plane design for high-current accelerator rails, and stackup and via structure definition
- 8+ years of package layout experience on high-performance designs, including 2.5D / 3D and multi-die packages (CoWoS, EMIB, InFO, fan-out, or equivalent interposer technologies)
- Hands-on with industry-standard package layout tools (Cadence Allegro Package Designer / SiP Layout, Siemens Xpedition Package Designer, or equivalent) and package DRC/LVS flows
- Demonstrated ability to work closely with architecture, physical design, SI/PI, thermo-mechanical, and OSAT partners to converge and sign off complex package designs
Full compensation packages are based on candidate experience and relevant certifications.
Compensation
Final offers depend on level, location, and skills relevant to the role. Additional compensation: equity grant per company guidelines; medical / dental / vision; 401(k); standard PTO.
Visa Sponsorship
DensityAI sponsors qualified candidates for H-1B, O-1, TN, E-3, and other employment-based visas, and we welcome applicants on F-1 OPT and STEM-OPT. Work authorization is required at start; we provide immigration support to secure or transfer status.
Export Controls
Aspects of this role may involve access to information subject to U.S. export controls (EAR/ITAR). We may discuss licensing or scope adjustments during the interview.
Equal Opportunity
DensityAI is an Equal Opportunity Employer. We do not discriminate on the basis of race, color, religious creed, national origin, ancestry, physical or mental disability, medical condition, genetic information, marital status, sex, gender, gender identity, gender expression, age (40+), sexual orientation, military or veteran status, pregnancy, or any other status protected by law. We comply with the California CROWN Act and provide reasonable accommodations on request.