PCIe Hardware System Engineer

Everpure (NYSE: P) has evolved from storage pioneer to data platform, closing fiscal 2026 with $3.7 billion in revenue, its first billion-dollar quarter, and accelerating growth into FY27. Our strategic agenda spans the companies defining the next era of technology - hyperscalers, AI labs, the AI hardware supply chain, data platform providers, and the broader AI ecosystem.

Apply here: https://job-boards.greenhouse.io/purestorage/jobs/8007293

The Role:

1. Own and drive the triage, root cause, and resolution of issues raised by internal teams, manufacturing, vendors, and customers.
2. PCIe Gen5 (must) and Gen6 interfaces
3. NVMe features
4. SMBus
5. Serve as the primary on-the-ground PCIe technical interface with our Taiwan-based
vendors and customers (JDM/ODM partners, SSD suppliers, flash controller vendors,
and enterprise customers), with on-site debug at vendor and customer facilities when
needed.
6. Operates as a self-motivated, self-directed engineer. Identify problems before they
escalate and drive them to closure across time zones with minimal supervision.
7. Ensure proper documentation and regular update to stakeholders throughout the triage
to resolution journey.
8. Guide the development of PCIe, NVMe, and SMBus validation test plan for early phase
chip bring-up and regression testing throughout the development cycle.
9. Lead failure analysis and root cause investigations to support field issues and customer escalations.
10. Leverage automation and AI to improve issue triaging, utilizing company-supported tools like Augment and Glean to facilitate agent development and harness advanced AI skills.
11. Provide technical leadership and mentorship to junior engineers as the Taiwan hardware team grows.

WHAT YOU'LL DO:

1. Over 5+ years of experience in advanced interface issue troubleshooting, root cause
analysis, and solution identification, encompassing complex system-level interactions
across host, PCIe, and CXL interfaces in enterprise server and SSD environments.
2. Developed and automated comprehensive validation and testing solutions.
3. BS in Electrical or Computer Engineering (or related field).
4. Proven track record in chip bring-up and product qualification.
5. Hands-on experience with PCIe Gen5/Gen6.
6. Proficient with test equipment including PCIe analyzer, Exerciser or Jammer, I2C
analyzer, and UART.
7. Experience with PCIe compliance testing (SIG) for SSD products.
8. Proficient in scripting with Python, BASH, and similar languages. Hands-on experience
in a Linux environment.
9. Demonstrated experience collaborating with vendors and/or customers in Taiwan (JD
M/ODM, SSD/flash-controller suppliers, or enterprise customers).
10. Self-motivated and self-directed, with a proven ability to operate independently as the
most senior local engineer without daily oversight.
11. Detail-oriented, analytical, process-driven, and customer-focused.
12. Thrive in fast-paced, evolving business environments.
13. Clear and effective communicator in Mandarin and English, both verbally and in writing.

Must have:

1. PCIe protocol and trace experience (Gen5; Gen6 a strong plus)
2. NVMe protocol hands-on (analyzer traces, NVMe-CLI, queue/command-level debug)
LTSSM PCIe, signal integrity knowledge and debug System interop experience
3. Hands-on with Teledyne LeCroy and/or Keysight PCIe analyzers
4. High-speed oscilloscope and BERT experience for PCIe physical-layer debug
5. Proven ability to drive cross-functional debug with FW, SoC design, and BIOS teams
6. Python scripting ,

Nice to have:

1. Firmware background (SSD/NVMe or PCIe FW)
2. CXL exposure
3. PAM4 / SerDes equalization tuning (Gen6-ready)
4. BIOS and Linux kernel storage stack familiarity
5. Customer joint qualification (JQ) experience with hyperscalers or enterprise customers
6. Automated regression / validation framework development (Python-based, shift-left) SSD hardware design experience
7. PCI-SIG compliance experience