PCIe Retimer 系統設計工程師
Summary
Engineer at Realtek in Hsinchu working on PCIe Retimer silicon: running system/functional validation, implementing and validating the PCIe Retimer spec, and building mass-production test plans and spec limits. Core stack: PCIe spec (Gen7 preferred), SerDes/high-speed interfaces, MATLAB/C/C++, OrCAD, and lab gear like oscilloscopes and BERTs.
工作內容：
a. PCIe Retimer system and functional validation
b. PCIe Retimer spec implement and validation
c. Developing PCIe Retimer mass production test plan and spec limit.
應徵條件：
a. 電子、資工、電機相關科系
b. 熟悉matlab、C/C++、OrCAD schematic和PCB layout reviewer之一
c. 具備 IC Validation、High-Speed Interface、SerDes PHY 或高速數位電路相關ASIC 驗證經驗者佳
d. 熟悉 PCIe spec，具 PCIe Gen7 相關經驗者佳; 有PCIe Retimer 開發、驗證及除錯經驗; 有PCIe Retimer 量產導入流程經驗之一
加分條件：
a. 具備 PCIe Gen3 / Gen4 / Gen5 / Gen6 / Gen7相關開發或驗證經驗
b. 熟悉 PCIe LTSSM、Link Training、Equalization、Retimer / Redriver 架構
c. 熟悉 NRZ/PAM4、CDR、CTLE、DFE、TX FIR、SSC、SRIS / SRNS
d. 熟悉 Oscilloscope、BERT、VNA、PCIe Protocol Analyzer 等設備
e. 具備 IC Bring-up、Silicon Debug、Compliance Test 經驗