PCIe validation Engineer

Key Responsibilities Pre-Silicon Develop and execute test plans for PCIe Gen3/Gen4/Gen5/Gen6 IP blocks and SoC-level integration Create directed and constrained-random tests targeting PCIe Transaction Layer (TLP), Data Link Layer (DLLP), and Physical Layer (PHY) functionality Perform protocol-level analysis using VIP (Verification IP) environments and bus functional models Debug RTL-level issues related to link training, power management (ASPM, L-states), equalization, and error handling Collab…