Connect over MCP — free, no account needed to search.Designs and implements high-performance AI SoC partitions from synthesis to tapeout, focusing on timing, power intent, and physical verification using Synopsys tools (Design Compiler, Fusion Compiler, IC Compiler II).
Mid- to senior-level physical design engineer focused on static timing analysis (STA), driving timing closure for multi-million-gate AI chip designs on advanced process nodes through signoff and tapeout. Day-to-day involves constraints (SDC), ECOs, corner analysis, and automation with Python, Perl, and Tcl at hybrid sites in Austin, Fort Collins, or Santa Clara.
Title: Static Timing Analysis (STA) / Timing Closure & Signoff Engineer Function: Physical Design – Timing Signoff Experience: 3 – 8 years of relevant STA / physical design experience Engagement: Engineering services…
Designs and implements high-performance CPU and AI/ML chip blocks from synthesis to tapeout, optimizing power, performance, and area using advanced EDA tools and methodologies.
Drive static timing analysis and closure for high-performance RISC-V CPUs and AI SoCs, collaborating with logic, DFT, and physical design teams using STA tools, SDC constraints, and Python/Perl/TCL scripting.
Designs and implements high-performance AI and CPU System-on-Chip layouts, optimizing power, performance, and area while collaborating with architecture and packaging teams.