Physical Design Engineer, SoC Static Timing Analysis

In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. In this role, you will contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering exceptional performance, efficiency, and integration.

The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

• Drive the sign-off timing convergence for high-performance designs.
• Set up the timing constraints, define the overall static timing analysis (STA) methodology, set up the STA infrastructure and sign-off convergence flows, and work closely with block owners throughout the project for sign-off timing convergence.
• Work with logic designers to drive architectural feasibility studies, develop timing, and explore RTL/design trade-offs for physical design closure.

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, a related technical field, or equivalent practical experience.
• 8 years of Physical Design experience including 2 years of experience with Static Timing Analysis (STA), including sign-off corner definitions, process margining, interface timing constraints, timing convergence, and setting frequency goals with technology scaling.
  
• Experience in constraints development for subsystems or full System-on-Chip (SoC) architectures.

Preferred qualifications:

• Proficiency with scripting languages commonly used in hardware automation (e.g., Tcl, Python, or Perl).
• Deep familiarity with ASIC physical design flows and methodologies, including synthesis, place and route (P&R), formal verification, and clock domain crossing (CDC).
• Solid fundamental knowledge of semiconductor device physics and transistor characteristics.