Physical Design Engineer
Summary
Designs and optimizes chip layouts for SoC projects using EDA tools like Genus and Innovus, focusing on performance, power, and physical verification checks.
- Support execution of physical design flow for SoC projects under guidance from senior engineers
- Assist in Place and Route (PnR) activities to help optimize chip layout, performance, and power
- Participate in basic sign-off checks including Design Rule Check (DRC), Layout Versus Schematic (LVS), and Static Timing Analysis (STA)
- Learn and use EDA tools such as Genus, Innovus, Quantus, and RedHawk for design implementation and analysis
- Support development of simple TCL and Perl scripts to automate routine design tasks
- Work closely with design and verification teams to understand issues and support resolution of design challenges
Required competencies and certifications
- Master’s /degree in Electrical Engineering or related field
- Proficiency in TCL and Perl scripting for design automation
- Expertise in handling EDA tools for SoC top-level physical design, including Genus, Innovus, Quantus, and Redhawk
- Experience physical design flow
Candidates who do not meet the above experience requirements but possess a background in back-end semiconductor design are encouraged to apply.
EA: 25C2690/ R23115755