Jul 26, 2022 Oct 25, 2026 3 views

Physical Design Layout Lead Engineer

Jul 26, 2022 Oct 25, 2026 3 views

ACTSearch Inc Physical Design Layout Lead Engineer

Description:

Responsible for RTL to GDSII flow

SDC/constrains understanding, generation, clock definition and timing closure

Synthesis with industry standard EDA tools

Low power analysis using UPF/CPF formats

Place and Route, clock tree synthesis

Static timing analysis

Formal equivalence checks

Layout verification and DRC analysis

Static/Dynamic IR analysis, power analysis, reliability analysis

Work with RTL engineers and tool vendor(s) for ongoing tool/methodology

improvement

Physical Design (Layout) Lead

Qualification:

MSEE with 10+ years of experience in implementation of ASIC/SoC in latest

process nodes

Experience in Logic synthesis, DFT insertion, STA, physical design, layout

verification and Tapeout

Proven track record in resolving PD issues like placement, congestion, CTS, routing

Good understanding of timing convergence process

Conversant with low power design implantation, IR/EM analysis

Hand on experience with industry standard place and route EDA tools (preferably

Cadence)

Experience handling tapeouts

Prior experience working for startups highly desirable

Description