PLL Characterization Engineer-High-Speed IO & Timing (Equity)
Summary
Senior engineer in Santa Clara designs and runs automated tests for high-speed input/output circuits and phase-locked loops, analyzing results to validate and improve silicon chips before mass production.
NVIDIA is seeking a senior PLL characterization engineer in Santa Clara to lead post‑silicon validation of high‑speed IOs and PLLs. You will develop automated ATE programs, work with DFT, and analyze large datasets to drive silicon from bring‑up to mass production.
The role requires deep PLL knowledge, extensive hands‑on testing experience, and strong Java/C++ automation skills, with collaboration across design, systems, and product teams. Equity and benefits are included.