Principal ASIC Integration Engineer

This is us

At Avenga, we believe that human creativity empowers technology that matters. Operating globally, our 6000+ specialists provide a full spectrum of services, including business and tech advisory, enterprise solutions, CX, UX and Ul design, managed services, product development, and software development.

This is the job

We are looking for an experienced Principal ASIC / SoC Architect to join an international engineering project focused on ASIC solutions for high-volume, cost-sensitive electronic products.

In this role, you will influence the complete ASIC development and production lifecycle: from system architecture, technology selection, and third-party IP evaluation through tape-out, manufacturing, testing, and yield optimization.

You will combine deep semiconductor expertise with a strong understanding of commercial and manufacturing considerations. Your decisions will directly affect product performance, power consumption, die size, system cost, production readiness, and supply-chain resilience.

The engagement is expected to last at least one year, with a possibility of extension for an additional year. We welcome candidates from across the EU, with priority given to professionals based in the Scandinavian countries. Candidates based in the US may also be considered.

The role involves regular travel to Denmark, potentially several times per month, as well as periodic travel to the US, other European countries, and Asia.

This is you

• You have at least 8 years of experience in ASIC microarchitecture, ASIC design, or SoC design within an electrical engineering environment.

• You have completed multiple successful ASIC or SoC tape-outs and have taken designs through the full development lifecycle.

• You have a strong understanding of ASIC and SoC architecture and microarchitecture, including system-level architectural trade-offs.

• You have hands-on experience evaluating, selecting, and integrating third-party semiconductor IP, including analog, compute, and memory IP.

• You understand semiconductor foundry processes, process nodes, and PDKs, as well as their impact on power, performance, cost, yield, and production readiness.

• You have solid knowledge of semiconductor packaging, assembly, testing methodologies, fault coverage, and production-test optimization.

• You understand yield fundamentals, including the relationship between die size and yield, silicon test data, production-line yield analysis, and yield optimization.

• You are familiar with Design-for-Cost, Design-for-Manufacturing, Design-for-Assembly, and Design-for-Yield principles.

• You understand wafer economics, OSAT operations, packaging and test costs, and the main drivers of semiconductor unit cost.

• You can evaluate technical decisions in the context of system BOM cost, manufacturing feasibility, production timelines, and supply-chain risk.

• You are comfortable collaborating with foundries, OSAT partners, IP vendors, and multidisciplinary internal teams.

• You are available for regular international business travel, particularly to Denmark.

This is your role

• Collaborate with electrical engineers to define requirements, evaluate architectural options, and develop ASIC specifications.

• Lead system-level trade-off analyses across performance, power, die size, unit cost, manufacturability, yield, and production readiness.

• Lead the technical evaluation, selection, and integration of third-party analog, compute, memory, and other semiconductor IP.

• Represent the electrical engineering team in technical discussions with foundries, OSAT partners, and IP vendors.

• Track semiconductor technology roadmaps and work with external partners to address manufacturing constraints and bottlenecks.

• Influence process-node and PDK selection based on performance, power, cost, yield, and foundry maturity.

• Drive Design-for-Cost, Design-for-Manufacturing, Design-for-Assembly, and Design-for-Yield considerations throughout the architecture and design process.

• Guide floorplanning, die-size optimization, pin count and placement, and packaging decisions.

• Provide technical input to semiconductor cost models covering wafer economics, OSAT location, packaging, test time, yield, and other unit-cost drivers.

• Partner with test and validation engineers to define strategies that maximize fault coverage while minimizing test time and production costs.

• Incorporate supply-chain resilience and multi-sourcing flexibility into architectural and manufacturing decisions.

• Analyze production-line yields and silicon test data with internal and external validation teams to identify opportunities for continuous improvement.

• Collaborate with technical and commercial stakeholders throughout the complete ASIC lifecycle, from architecture and technology selection to tape-out, manufacturing, testing, and yield optimization.
  

What awaits you at Avenga?

At Avenga, everyone matters. We provide equal opportunities in recruitment, career development, and leadership, regardless of race, ethnicity, gender identity, sexual orientation, disability, age, religion, or any other characteristic. We are committed to fostering a work environment where our diverse community of employees, candidates, and business partners actively shapes our growth. By bringing together people from different backgrounds and experiences, we build a workplace where everyone feels free to be themselves while honoring the boundaries of others.