Principal Design Engineer

Open 32d

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Responsibilities:

Contribute to AMS design for High-speed Memory PHYs.
Responsible for major sub-system of Memory PHY like Tx, Rx or Clocking
Understand system specification, define design micro-architecture, and define the design hierarchy.
Participate in technical discussions with cross function teams
Fully accountable for AMS design quality and schedule
Own the design progress, identify potential risks, and mitigation plan for sub-system
Mentor and provide technical guidance to team working in the projects.
Contribute to AMS methodology improvements to boost efficiency and productivity.

Requirements/Qualifications:

Bachelor's/Master's degree in Electronics/Electrical Engineering. Specialization in VLSI/Micro-electronics is preferred.
7+ years of Analog Mixed Signal design experience
Sound knowledge on AMS design techniques and circuit architecture
Strong experience on high-speed circuits like Tx, Rx, CTLE, Amplifiers, Samplers
Exposure to Serdes, DDR, HBM technologies
Should have knowledge on all aspects of Mixed Signal IP design.
Experience on working with AMS verification and logic designers to achieve AMS circuit requirements
Hands-on experience on block, IP and system level design.
Should have involved in designing multiple IPs from Specification to Productization
Experienced in lab debugs on AMS IPs
Excellent communication and interpersonal skills, demonstrate teamwork and collaboration skills.