Principal Hardware Application Engineer

Customer design engagement: Serve as the primary hardware technical focal for strategic accounts. Drive design-in activities from schematic review through board bring-up, EDVT, and mass production.

• Schematic and layout review: Review customer PCB schematics and layout files for Marvell DC switch platforms. Provide design guidance on component selection, power sequencing, clock distribution, and high-speed signal routing.

• SI/PI analysis: Perform or coordinate signal integrity and power integrity simulations (pre- and post-layout) for high-speed Ethernet interfaces at 800G, 1.6T, and beyond. Evaluate channel performance, SerDes tuning (Tx EQ / Rx CTLE), and PAM4 link margin.
• Board bring-up and debug: Support hardware bring-up at customer sites and in Marvell's Taipei lab. Debug L1 issues including SerDes link training, power integrity, thermal, and interface failures.
• Design documentation: Author and review hardware design guides, application notes, schematic checklists, and layout guidelines for internal and external use.
• Cross-functional collaboration: Join-in EE/ME/SI/PI design reviews with Marvell's global hardware engineering team. Represent customer requirements and feed back design insights to silicon and platform teams.
• Technology exploration: Ramp up knowledge on next-generation interconnect technologies including UALink, ESUN, CPO (Co-Packaged Optics), and 224G SerDes. Contribute to internal training and knowledge-sharing forums.
• Supplier chain engagement: Leverage Taiwan's comprehensive supply chain ecosystem — PCB materials, thermal solutions, power components, connectors, and cabling — to optimize platform designs.