Process Integration Engineer

PH-012 | Founding Technical Staff | Boston, MA | Onsite | $125K – $180K base + equity

About Prahelika

Prahelika is building the domestic integration layer: 3D systems in which III-V semiconductors, state-of-the-art silicon, and novel interposers are stacked into one device, each doing what it does best. We co-design the signal path, the power tier, the thermal path, and the manufacturing process, so dies from any foundry become a system that silicon alone cannot deliver. Our first 3D systems serve defense radar and low-Earth-orbit satellite communications; the same platform extends to power electronics, data-center compute, and photonics. Backed by top-tier investors and built by engineers who demonstrated every tier of the stack as measured hardware before the company existed, Prahelika owns the layer between the transistor and the machine. Ultimate electronics through integration.

The role

Whoever owns a design here sees it through fabrication, packaging, measurement, shipping, and the next revision. One of our four founding axioms is to vertically integrate: we own the key processes and manufacture onshore. A process is recipes and yield, and it cannot be licensed. Today our integration processes run on university and partner tools, in the founders' hands. That cannot stay true while the company grows.

You will take them over. As our first process engineer, you own the recipes for our 3D integration flow, from substrate preparation and cavity or via formation through die placement, bonding, dielectric build-up, and redistribution, on the tools we use today, and you carry them into our own facility when it opens. You run the lots, keep the yield data, and are the reason the process survives the move.

Required qualifications

• M.S. or Ph.D. in Materials Science, Electrical Engineering, Chemical Engineering, or Physics, with 3+ years of hands-on process development in a cleanroom, on a process that reached a stable yield. Equivalent practical experience may substitute for the degree requirement.

• Direct tool experience across the packaging unit steps: lithography, thin-film deposition and plating, wet and dry etch, laser processing, die placement and bonding, and thin-film dielectric lamination or spin-on.

• Disciplined process ownership: run cards, split lots, SPC, and a written recipe someone else can run.

• Hands-on experience in at least two of the following:

  • Die embedding, die-to-wafer, or wafer-to-wafer bonding (thermocompression, hybrid, adhesive, or die-attach film) with measured alignment and bond-integrity data.

  • Redistribution-layer build-up: semi-additive patterning, via formation, seed and electroplating, dielectric cure and reliability.

  • Processing of non-silicon substrates: glass, ceramic, diamond, or compound semiconductor, including handling and thermal-budget constraints.

  • Process transfer between tool sets or facilities, with the yield data to show it worked.

• This role involves work that may be subject to U.S. export-control laws. Prahelika assesses access requirements for the specific work and, where needed, evaluates available government authorization options before granting access to controlled technology. Program assignments are subject to applicable legal requirements.

Preferred qualifications

• University or shared-facility cleanroom experience (MIT.nano, Georgia Tech IEN, or similar), where you ran your own tools.

• Failure analysis on assembly defects: cross-section, X-ray, acoustic microscopy.

Responsibilities

• Develop and own the recipes for our integration flow on the university and partner tools we use today, and run the lots for our first products.

• Document every step so it survives you: run cards, travelers, SPC, and the split-lot data behind each recipe decision.

• Drive yield learning with the integration, thermal, and reliability engineers, and close root causes into the recipe and the design rules.

• Work with the Director of the Integration Facility on tool selection and cleanroom requirements, and lead the process transfer into our own line.

• Establish the process capability data that becomes the manufacturing rules in Prahelika's design kit.

How we work

• Engineers here work across the stack. Siloed circuit, device, and package engineers do not thrive at Prahelika; you will be expected to understand the neighboring disciplines well enough to argue with them.

• AI is a cornerstone of how we engineer. You will build your own workflows with tools such as Claude, ChatGPT, or Codex, compatible with Prahelika's AI ecosystem, with physically grounded checks on what they produce.

• No one is asked to cut a corner they would be ashamed to defend. If a deadline can only be met by skipping a reliability test, the deadline moves, and the engineer who refuses to sign off on something unsound is protected, not punished.

• Credit and authorship follow contribution, not seniority. If your name belongs on the work, it is there.

• Excellence of mind and body is a working condition, not a reward for finishing. Tired decisions end up in hardware; we expect you to sleep, train, and step away, and we do not mistake hours logged for work delivered.

Compensation and benefits

• $125K – $180K base salary plus founding-team equity. Final compensation depends on experience and skills.

• Full medical, dental, and vision coverage with HSA; 401(k) with 4% company match; daily meals.

How to apply

Apply using the form for this role. If available, please include a brief description of one project that best represents your work on this kind of problem; we read that more closely than a cover letter.

Prahelika is an equal opportunity employer. We hire on demonstrated ability, without regard to any protected characteristic.